library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all; 

use work.gestioneBMP.all;
use work.faw_types.all;
ENTITY Telecamera_simulata_TestBench IS
END Telecamera_simulata_TestBench;

ARCHITECTURE behavior OF Telecamera_simulata_TestBench IS 
-- Component Declaration for the Unit Under Test (UUT)
  COMPONENT TestingUnit
       Port ( clk_tu : in  std_logic;
					reset_tu : in std_logic;
					pixel_merged_tu : in  std_logic_vector (23 downto 0);
					frame_valid_tu : inout  std_logic;
					line_valid_tu : inout  std_logic;
					pixel_valid_tu : inout  std_logic;
					left_out_tu : inout  STD_LOGIC_VECTOR (7 downto 0);
					right_out_tu : inout  STD_LOGIC_VECTOR (7 downto 0);
               i_tu : inout COUNTER_ROWS;
               j_tu : inout COUNTER_COLUMNS;
               counter_cc_ref_tu : out  COUNTER_CENTRALS;
					enable_cc_ref_tu : out  STD_LOGIC;
               dina_tu : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
               addra_tu : INOUT STD_LOGIC_VECTOR (N_BIT_BR_CENTRALS-1 downto 0);
               enb_tu : inout STD_LOGIC;
               addrb_tu : inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
               doutb_tu : out std_logic_vector(7 downto 0);
               pixels_centrali_target_tu : out TCPSR_SR_DATA_BUS;
                        
                        --solo per test
                        br_sr_bus_tu : inout std_logic_vector(7 downto 0); 
                        addrb_tcpc_tu : inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
                        addra_tcpc_tu : inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
--                      en_rspsrc_tu :  inout SR_ENABLE_BUS;
--                      ena_rspbr_tu : out BR_ENABLE_BUS;
--                      wea_rspbr_tu : out BR_WEA_BUS;
--                      addra_rspbr_tu : out RSP_BR_ADDRESS_BUS;
--                      dina_rspbr_tu : out STD_LOGIC_VECTOR(7 DOWNTO 0);
--                      enb_rspbr_tu : out BR_ENABLE_BUS;
--                      addrb_rspbr_tu : out RSP_BR_ADDRESS_BUS;
--                      
                        we_tspsrc_tu : inout TARGET_SR_ENABLE_ROWS;
                        we_rspsrc_tu : inout SR_ENABLE_ROWS;
                        data_out_tspsrc_tu: inout TSPSRC_SR_DATA_BUS;
                        data_out_rspsrc_tu: inout RSPSRC_SR_DATA_BUS
                        );

  END COMPONENT;
--Inputs
  signal clk : std_logic := '0';
  signal reset:std_logic:='0';
--Output
--  signal data_out_rspbr : RSPSR_SR_DATA_BUS;
  signal pixel_merged : std_logic_vector (23 downto 0):= (others => '0');
  signal left_out : std_logic_vector(7 downto 0);
  signal right_out : std_logic_vector(7 downto 0);
  signal frame_valid: std_logic;
  signal line_valid: std_logic;
  signal pixel_valid: std_logic;
  signal i: COUNTER_ROWS;
  signal j: COUNTER_COLUMNS;
  signal we_rspsrc : SR_ENABLE_ROWS;
  signal data_out_rspsrc : RSPSRC_SR_DATA_BUS;
  signal counter_cc_ref :  COUNTER_CENTRALS;
  signal enable_cc_ref :  STD_LOGIC;
        signal dina : STD_LOGIC_VECTOR(7 DOWNTO 0);
        signal addra :  STD_LOGIC_VECTOR (N_BIT_BR_CENTRALS-1 downto 0);
        signal addrb : STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
        signal doutb : std_logic_vector(7 downto 0);
  signal pixels_centrali_target : TCPSR_SR_DATA_BUS;
  
        signal br_sr_bus : std_logic_vector(7 downto 0); 
        signal addrb_tcpc :  STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
        signal addra_tcpc :  STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
  
  signal we_tspsrc :  TARGET_SR_ENABLE_ROWS;
	signal data_out_tspsrc: TSPSRC_SR_DATA_BUS;
  
--      signal en_rspsrc :  SR_ENABLE_BUS;
--      signal ena_rspbr :  BR_ENABLE_BUS;
--      signal wea_rspbr :  BR_WEA_BUS;
--      signal addra_rspbr :  RSP_BR_ADDRESS_BUS;
--      signal dina_rspbr :  STD_LOGIC_VECTOR(7 DOWNTO 0);
--      signal enb_rspbr : BR_ENABLE_BUS;
--      signal addrb_rspbr : RSP_BR_ADDRESS_BUS;

  ----------------------------------
--img_array   : img_array_t(0 to X_SIZE-1, 0 to Y_SIZE-1);
  signal X_SIZE : integer :=640;
  signal Y_SIZE : integer :=480;
  
  
  ----------------------------------
-- Clock period definitions
  constant clk_period : time := 0.11 us;
BEGIN
  -- Instantiate the Unit Under Test (UUT)
       uut: TestingUnit PORT MAP (
            clk_tu => clk,
				reset_tu=>reset,
				pixel_merged_tu=>pixel_merged,
            left_out_tu=>left_out,
                           right_out_tu=>right_out,
                                frame_valid_tu=>frame_valid,
                                line_valid_tu=>line_valid,
                                pixel_valid_tu=>pixel_valid,
                                i_tu=>i,
                                j_tu=>j,
                                counter_cc_ref_tu=>counter_cc_ref,
                                enable_cc_ref_tu=>enable_cc_ref,
                                dina_tu=>dina,
                                addra_tu=>addra,
                                doutb_tu=>doutb,
                                addrb_tu => addrb,
                --              en_rspsrc_tu =>en_rspsrc,
                                we_rspsrc_tu=>we_rspsrc,
                                data_out_rspsrc_tu =>data_out_rspsrc,
                                pixels_centrali_target_tu=>pixels_centrali_target,
                                we_tspsrc_tu=>we_tspsrc,
                                data_out_tspsrc_tu=>data_out_tspsrc,
                                --solo per test
                                br_sr_bus_tu=>br_sr_bus, 
                           addrb_tcpc_tu=>addrb_tcpc,
                           addra_tcpc_tu=>addra_tcpc 
                                
--                              ena_rspbr_tu=>ena_rspbr,
--                              wea_rspbr_tu=>wea_rspbr,
--                              addra_rspbr_tu=>addra_rspbr,
--                              dina_rspbr_tu=>dina_rspbr,
--                              enb_rspbr_tu=>enb_rspbr,
--                              addrb_rspbr_tu=>addrb_rspbr
                );
-- Clock process definitions
 CLOCK_process:process
 begin
 clk <= not(clk);
 wait for clk_period/2 ;
 end process ;
        
        
read_file_data: process
        
                 variable LEFT_IN_VAR : STD_LOGIC_VECTOR(7 downto 0);
       begin
                                
                 ReadFile("image/TeddyMerge.bmp"); 
                
                 GetWidth(X_SIZE);
                 GetHeigth(Y_SIZE);
     
								reset<='1';
                        wait for clk_period;
								reset<='0';
					--			wait for clk_period;
                        
                        for y in 0 to Y_SIZE-1 loop
                                        for x in 0 to X_SIZE-1 loop
                                                GetPixel(x, y,pixel_merged);
                                                wait for clk_period ;
                    end loop;
                                
                                        pixel_merged<="000000000000000000000000";
                                        wait for 2*clk_period;
         end loop;
        
        WriteFile("image/bmp_output.bmp");
        end process;
        
END;